1. Field of the Invention
The present invention relates to output circuits and, particularly, to an output circuit suitable for use to quickly turn off an output voltage of a source follower constituted by a n-channel MOS transistor (nMOS).
2. Description of Related Art
In output circuits, a source follower constituted by nMOS is used as a high-side switch in some cases. The source follower is turned on if its gate is supplied with a voltage equal to or higher than a supply voltage Vcc plus a gate threshold voltage α. The source follower, on the other hand, is turned off if the gate is discharged completely. In order to quickly turn off the source follower, it is necessary to use a discharge circuit for discharging the gate at high speed. Further, when the source follower is used for a power switch for car, for example, a distance between a control circuit of the power switch and a load is relatively long. This can cause a voltage difference between a ground level of the control circuit of the power switch and the ground level of the load. Thus, a discharge circuit to short the gate and source of the source follower is needed to completely turn off the source follower.
FIG. 6 shows an example of a conventional output circuit. The output circuit is composed of a gate driver circuit 1, source follower 2, discharge circuit 3, and discharge circuit 4. The gate driver circuit 1 generates control signals “a” and “b” according to an input signal “in”. The source follower 2 is constituted by an enhancement nMOS. It is turned on if the control signal “b” is applied to its gate while a first supply voltage Vcc is applied to its drain to supply an output voltage Vo to a load, which is not shown, through its source.
The discharge circuit 3 is composed of a current limiter 5 and an enhancement nMOS 6. The drain of the nMOS 6 is connected to the gate of the source follower 2 via the current limiter 5. The nMOS 6 is turned on if the control signal “a” is applied to its gate while a second supply voltage Vdd is applied to its source. The current limiter 5 is constituted by a resistor and so on to limit the current of the nMOS 6. The discharge circuit 4 is constituted by an enhancement nMOS. The drain of the discharge circuit 4 is connected to the gate of the source follower 2, and the source is connected to the source of the source follower 2. The nMOS of the discharge circuit 4 is turned on if the control signal “a” is applied to its gate.
FIG. 7 is a time chart to explain the operation of the circuit of FIG. 6. The vertical axis represents voltage, and the horizontal axis represents time. The operation of the output circuit is explained below with reference to FIG. 7.
At t1, the input signal “in” and the control signal “a” change from high (for example, a first supply voltage Vcc) to low (for example, a second supply voltage Vdd), and the control signal “b” changes from low to Vcc+α, where α is a gate threshold voltage of the source follower 2, for example, and a voltage increase to turn on the source follower 2. At t2, a gate voltage G of the source follower 2 changes from low to Vcc+α. The source follower 2 is thereby turned on to output an output voltage Vo, which is close to the first supply voltage Vcc, through its source. The discharge circuit (nMOS) 4 is thereby turned off. The nMOS 6 of the discharge circuit 3 is also off.
At t3, the input signal “in” and the control signal “a” change from low to high, and the side of the gate control circuit 1 for outputting the control signal “b” is at high impedance. The nMOS 6 of the discharge circuit 3 is turned on, and the gate of the source follower 2 is discharged through the current limiter 5 and the nMOS 6. At t4, after a delay time td from t3, when the gate voltage G of the source follower 2 decreases to the same level as the first supply voltage Vcc, the output voltage Vo starts decreasing. Then, at t5, when the output voltage Vo reaches a level of the first supply voltage Vcc minus the gate threshold voltage h of the discharge circuit (nMOS) 4, the discharge circuit 4 is turned on. The gate of the source follower 2 is thereby discharged also through the discharge circuit 4. At t6, the discharge is completed and the gate voltage G decreases to low, and the output voltage Vo thereby becomes low. An output current Io changes in the same way as the output voltage Vo.
A conventional power switch for car generally has the configuration shown in FIG. 8. The power switch 10 is composed of an input terminal 11, gate driver circuit 12, source follower 13, and output terminal 14. The power switch 10 is configured to receive the first supply voltage Vcc and the second supply voltage Vdd, and actively uses the second supply voltage Vdd.
Recently, it is often required to configure an output circuit in a package with a small number of pins to reduce the package size. In such a case, a power switch having the configuration shown in FIG. 9 is used. The power switch 10A is configured to receive the first supply voltage Vcc only and have an input terminal 11 connected to an external device 20. The external device 20 includes a control terminal 21 and a nMOS 22. In the power switch 10A, the source follower 13 is turned on if a control signal is inputted to the control terminal 21 to turn on the nMOS 22, and the input terminal 11 thereby changes to low (the second supply voltage Vdd). The second supply voltage Vdd is then applied to the power switch 10A via the input terminal 11.
Another example of output circuit of this kind is introduced in Japanese Unexamined Patent Application Publication No. 03-198421. This output circuit has a switch circuit shorting the gate and source of the source follower as a circuit to keep the source follower off. Thus, the source follower is not turned on even if a negative voltage is applied to the output terminal.
However, the above conventional output circuits have the following problems.
In the output circuit of FIG. 6, the gate of the source follower 2 is discharged through the discharge circuit 3 from t3 when the control signal “a” changes from low to high to t5 when the discharge circuit (nMOS) 4 is turned on. Since the discharge is slow in this time period, the delay time td from t3 to t4 when the output voltage Vo starts decreasing is long. This causes the problem that the output circuit cannot meet the requirement of high-speed switching of the source follower 2. On the other hand, too rapid switching causes noise on the first supply voltage Vcc. Hence, it is necessary to turn off the switch follower 2 so that the output voltage Vo decreases relatively gradually. Further, since the discharge circuit 3 is connected to the ground, it requires a package with a large number of pins. This causes that the output circuit is not applicable to the power switch with the configuration shown in FIG. 9.
Furthermore, if a short circuit occurs in the load for some reason, the output voltage Vo is kept at Vdd (the second supply voltage) as shown in FIG. 10. In this case, an excessively large current flows in the source follower 2, which can break down the source follower 2. It is therefore preferred to shorten the delay time td.
Further, in the power switch 10A shown in FIG. 9, when the nMOS 22 of the external device 20 is off, the second supply voltage Vdd is not applied to the power switch 10A. It is thus necessary to configure the output circuit which does not require the second supply voltage Vdd while the source follower 2 is off.
Furthermore, the output circuit described in Japanese Unexamined Patent Application Publication No. 03-198421 has the problem that the source follower is turned off so quickly that noise can occur on the supply voltage.